Algorithmic test pattern generator, with built-in-self-test (BIST) capabilities, for functional testing of a circuit

ABSTRACT

A test system includes a test data generator to provide test data (e.g., a test pattern) to a subject circuit (e.g., a digital television video circuit). The test data is functionally to verify the subject circuit. The functional verification of the subject circuit is performed utilizing an output of the subject circuit generated responsive to the test data in accordance with an operational functionality of the subject circuit. The test data generator is also coupled to provide the test data to a built-in self-test (BIST) circuit so as to enable the built-in self-test circuit to receive the test data.

[0001] The present application claims the benefit of the filing date ofprovisional US patent application Ser. No. 60/176,434 filed Jan. 14,2000.

FIELD OF THE INVENTION

[0002] The present invention relates generally to the field of circuittesting and, more specifically, to an algorithmic test patterngenerator, and with built-in self-test capabilities, for the functionaltesting of a circuit within, for example, a communications device.

BACKGROUND OF THE INVENTION

[0003] One of the most expensive and time-consuming aspects ofintegrated circuit design and manufacture is the production test phase.Upon fabrication, each device should be fully tested before it can besold. Coarse tests are used to filter grossly failing devices. Moredetailed tests are typically required to detect devices that operatelargely as designed, but are still not fully functional. As circuitsbecome more complicated, it is becoming increasingly difficultadequately to exercise (e.g., control) and monitor (e.g., observe) allthe internal parts of a circuit from outside a device within which sucha circuit operates. To address these difficulties, methods to performbuilt-in self-test (BIST) have been developed. To achieve BIST, elementsare added internally to a circuit design for the exclusive purpose oftesting the circuit. At a test stage, these blocks are exercised andafter a known period of time, a determination can be made if sections ofthe circuit being controlled operate in an intended manner and withintended functionality.

[0004] The testing of circuits in communication devices is particularlychallenging in view of the nature of data processed by suchcommunication devices. To illustrate this point, it is useful toconsider the functioning of a typical communications system. At a firststage, a communications system acquires data (e.g., a message) andmodulates it. A second stage encodes the acquired data for transmissionover a communications channel. At the other end of the communicationschannel, a receiving communications system decodes the channelinformation and demodulates this data to recover the original message.To fully and properly test a complex communications device, long streamsof detailed and exact data, which accurately represent data that may betransmitted and/or received by the communications device over acommunications channel, should be supplied to a communications deviceduring the test phase. Typically, in the prior art, specializedequipment specific to each type of system and communication channel isnecessary both to supply such test data and determine if a recoveredmessage is correct. When communications devices form part of a printedcircuit board (PCB), these devices may be difficult to access directlyas the input data is typically supplied to the communications device viaa path including several other integrated circuits.

[0005] Consider further that in many cases, the complete data streams orpackets must be supplied to a communications device before a transmitterthereof performs any valid operations. Such data streams can be verylong, and even sometimes exceed the storage capability of standard testequipment.

[0006] Additionally, there is also often a need to check if an entireproduct incorporating a communications device is working properly andsupports certain standards. In such cases, a quick and simple test isoften all that is required to test digital video applications (e.g.,SMPTE-259M, SMPTE-292M, and the Digital Video Interface (DVI)).

SUMMARY OF THE INVENTION

[0007] A method of generating test data to functionally verify a circuitthat detects a data selection signal and, responsive to the dataselection signal, presents test data to verify the circuit wherein thepresenting of the test data includes composing the test data utilizing acombination of algorithmically generated data and stored data.

[0008] Other features of the present invention will be apparent from theaccompanying drawings and from the detailed description which follows.

Brief DESCRIPTION OF THE DRAWINGS

[0009] The present invention is illustrated by way of example and notlimitation in the figures of the accompanying drawings, in which likereferences indicate similar elements and in which:

[0010]FIG. 1A through 1C (FIG. 1) is an embodiment of an algorithmictest pattern generator that includes built-in self-test (BIST)capabilities.

[0011]FIG. 2 is a flowchart illustrating an exemplary method by which apattern generator state machine may be programmed.

[0012]FIG. 3 is a flowchart illustrating an exemplary method ofgenerating test data to functionally verify a circuit.

[0013]FIG. 4A through 4C (FIG. 4) is a block diagram illustrating anexemplary internal structure of a pattern generator for application in abroadcast quality serial digital television video system.

[0014]FIG. 5A through 5C (FIG. 5) illustrates exemplary sample valuesthat may be utilized by the generator illustrated in FIG. 4 to testdifferent component standards.

[0015]FIG. 6A through 6B (FIG. 6) is a flowchart illustrating anexemplary programmed flow sequence that may be implemented by thegenerator illustrated in FIG. 4.

[0016]FIG. 7 is a flowchart illustrating an exemplary method ofperforming BIST operation.

[0017]FIG. 8 is a block diagram illustrating details regarding anexemplary comparator system.

[0018]FIG. 9 is a flowchart illustrating an exemplary programmed methodaccording to which a BIST state machine may operate.

[0019]FIG. 10 is a block diagram illustrating an exemplary arrangementby which a complete test of transmit, channel and receive units of acommunications device may be performed.

[0020]FIG. 11 is a block diagram illustrating an integrated circuit thatincorporates a test pattern generator with integrated BIST controlcircuitry.

DETAILED DESCRIPTION

[0021] An algorithmic test pattern generator, with built-in self-test(BIST) capabilities, to verify a circuit and a system including such acircuit, and a method of operating such an algorithmic test patterngenerator, are described. In the following description, for purposes ofexplanation, numerous specific details are set forth in order to providea thorough understanding of the present invention. It will be evident,however, to one skilled in the art that the present invention may bepracticed without these specific details.

[0022] An exemplary embodiment of algorithmic test pattern generatorthat may be utilized as an internal data pattern generator for multiplecommunications standards, for which fully valid data streams may bealgorithmically generated, is disclosed. The test pattern generator alsoaccepts error correction data from an internal control block that isutilized to implement built-in self-test (BIST) functionality. In oneembodiment, the present invention allows a test mode to be implementedfor a device wherein the device is clocked at a fully operational speed.

[0023] The present invention finds particular application, but is notlimited to, the testing of circuits for utilization in communicationsystems. Typically, communication systems and channels communicate dataeither as streams or packets of data. In streamed systems, there is acontinuous transmission of data. In packet systems, data is fracturedinto groups. The present invention contemplates generating test data fortesting both streamed systems and packet systems. Specifically, forstreamed systems, the present invention, in one embodiment, utilizes afinite portion of a stream and repeats it. For packets systems, thepresent invention may, in one embodiment, generate one or more packetsand apply such packets to the communications system.

[0024]FIG. 1 is a block diagram illustrating an algorithmic test patterngenerator 10, according to an exemplary embodiment of the presentinvention, which also includes built-in self-test (BIST) capabilities. Adata input register block 12 is shown to receive a pattern select signal14, a system clock 16 and a reset signal 18. The register block 12includes two storage registers namely a buffer register 20 and a patternselection register 22, as well as a pattern change detector 24, fromwhich is output a change pattern signal 26.

[0025] Pattern generation components of the generator 10 including: amode select module 28, a pattern generation state machine 30, a packetcounter 32, a sample counter 34, a pattern generator state register 36,pattern lookup select blocks 38, an algorithmic packet/sample generationmodule 40, lookup tables for pattern generation 42, and a pattern outputregister 44.

[0026] BIST components of the generator 10 include a BIST state machine46, lookup tables for BIST 48, a checksum selection module 50, achecksum comparator 52, and a BIST register 54.

[0027] Operation of each of these components will now be discussed infurther detail below with references to flow charts.

[0028] Generation of Algorithm and Stored Portions

[0029]FIG. 2 is a flowchart illustrating, at a high-level, an exemplarymethod 60 by which a pattern generation state machine 30 may beprogrammed, and lookup tables for pattern generation 42 populated. Atblock 62, a suitable data pattern or data sequence (e.g., >100,000samples) is selected. For the testing of many communications standards,either a number of sequence formats of the relevant standard exist, ordifferent data sequences are required to fully exercise a device to testfor standards compliance. For such standards, a single generator 10 maybe implemented and the lookup tables 42 may be utilized to supply of thegenerator 10 with information required to generate a full data sequencefor multiple test patterns.

[0030] At block 64, the sample test pattern (or sequence) is analyzed togenerate an algorithm that minimizes the data storage or generationlogic (e.g., the algorithmic packet/output generation module 40). Testpattern data generally exhibits a high degree of regularity or containsrepeated sequences that are easily recognized by inspection.Alternatively, these repetitive data sequences can be defined within astandards document issued for such test purposes by a standardsorganization such as the American National Standards Institute (ANSI)or, as in the present case concerning television video test signals, theSociety of Motion Picture and Television Engineers (SMPTE). In oneexample; one line of video picture data is comprised of 1,71610-bit-long, data sample words.

[0031] These samples include 858 representing the picture luminance (Y)value, 429 each representing the two different color differencecomponent (Cr and Cb) values for a total of 1,716 samples organized in arepetitive pattern, Y, Cb, Y, Cr, etc. Of the total number of samples,1,440 samples comprise the active picture line data: 720 luminance (Y)samples and 360 each of the color difference samples (Cr and Cb). Theseare similarly interleaved, Y, Cb, Y, Cr, etc. The remaining 276 samplescomprise other repetitive sequences of data that are used foridentification of the beginning and ending of the line or containsamples representing the horizontal blanking interval portion of thetotal video line's duration.

[0032] Specifically, a line of active picture chrominance and luminancedata samples representative of one such test pattern is comprised of theY, Cb, Y, Cr sequence: 300, 198, 300, 198 . . . (hexadecimalrepresentation) a total of 360 times. A sequence of data samples, 3FF,000, 000, XYZ occurs twice (where XYZ may be one of eight unique datawords used for identification purposes). The remainder of the 268 datasamples comprise a sequence: 040, 200, 040, 200, . . . , representingthe horizontal blanking interval data.

[0033] An algorithm may be programmed into the algorithmic packet/samplegeneration module 40 discussed above (with reference to FIG. 1).Typically, data patterns or sequences within a test pattern which havelong repeated sequences, or which may be easily generatedalgorithmically (as discussed just above), may be very efficiently“compressed” by way of algorithmic representation.

[0034] At block 66, values are stored in the lookup tables 42 for pointsin the data pattern or sequence where it is not possible toalgorithmically generate data, with an appropriate lookup or an index,so as to enable recall of such values for regeneration of a testpattern.

[0035] Algorithmic Generation of Test Data

[0036]FIG. 3 is a flowchart illustrating a method 70, according to anexemplary embodiment of the present invention, of generating test datato functionally verify a circuit. In one embodiment, such a circuit maybe included within an integrated circuit device for the processing andtransmission of digital television signals. It will be appreciated thatthe present invention is not limited to such an application. Further,while the test data is below described as comprising a “test pattern”,it will be appreciated that this test pattern may constitute a stream ofdata or packets of data.

[0037] The method 70 commences at block 72 with the activation of thegenerator 10, for example by the assertion of an enable signal 90illustrated in FIG. 1. At block 74, where the generator 10 is capable ofgenerating multiple patterns, a pattern to be generated by the generator10 is selected utilizing, for example, the pattern select signal 14. Asdescribed above, the pattern select signal 14 provides input to the datainput register block 12. At block 76, the pattern selection signal 14 isclocked through the buffer register 20 on a first clock signal. Thepattern selection register 22 may store an indication of a previouslyselected pattern. The buffer register 20 and the pattern selectionregister 22 both provide input to the pattern change detector 24, thusallowing the detector 24 to detect a change in pattern selection.Responsive to a detection of a change in pattern selection, the patternchange detector 24 assets a change pattern signal 26, which thenoperates to reset to the pattern generation state machine 30.

[0038] At block 78, the mode select module 28 monitors the patternselection register 22, and decodes its output to determine a selectedtest pattern to be generated. At block 80, the mode select module 28outputs a number of signals indicating the exact pattern(s) to begenerated, to the pattern generation state machine 30. These signalsincluded, for example, a pattern type signal 92 and/or a packetselection signal 94.

[0039] At block 82, the pattern generation state machine 30 starts andinitiates sample, packets and lookup signals. For example, these signalsmay include a clear/increment sample counter signal 96, aclear/increment packet counter signal 98 and a selected specialsamples/packets signal 100. These signals are input to the packetcounter 32, which outputs the packet count signal 102, and to the samplecounter 34 that outputs a sample count signal 104. The packet countsignal 102 and the sample count signal 104 are then shown to again befed back as input to the pattern generation state machine 30, so as toenable the state machine 30 to track in the location in a test patterndata sequence and to appropriately transition between states accordingto its programming.

[0040] The pattern generation state machine 30 tracks the location inthe test pattern data sequence, utilizing the signals described above,and decides which data is to be supplied next as part of the output testpattern data sequence. At one end of such a test pattern data sequence,the pattern generation state machine 30 resets the entire sequence, orprogresses to a subsequent sequence. As described, the packet counter 32and the sample counter 34 are utilized to track a location within thetest pattern data sequence. It will be appreciated that, forparticularly complex patterns, additional counters may be added toenable the state machine 30 to track a current location within a testpattern data sequence.

[0041] As also illustrated in FIG. 1, the algorithmic packet/samplegeneration module 40 also receives the packet count signal 102, thesample count signal 104, and the select special samples/packets signal100 as input. The algorithmic packet/sample generation module 40 is athus controlled by the pattern generation state machine 30, the packetcounter 32, and the sample counter 34 to algorithmically generate data(i.e. algorithmic packet/samples 106) for input to the patterngeneration state machine 30.

[0042] The pattern generation state machine 30 is also shown to output apattern lookup control signal 108 to the pattern lookup select blocks 38that, utilizing increment signals, output a selected pattern lookup datasignal 110 that indexes into the lookup tables for pattern generation42. The data from the lookup tables 42 is controlled by the patternlookup select blocks 38 as more than one lookup table may be utilizedfor complex test pattern data streams. Pattern data 111 from the lookuptables 42 is provided as input to the pattern generation state machine30. Typically, the lookup tables 42 content consists of the unique datasamples, and not any patterns or data sequences as such. While, atvarious points within a test pattern data stream, special data sequencesmay be required, these are typically generated by the pattern generationstate machine 30. Pattern data 111 or 114 may be subjected to additionalprocessing such as filtering or dithering to create more complex testpatterns.

[0043] From the above discussion, it will be appreciated that thepattern generation state machine 30 is able selectively to composepattern data 112 (for output to the pattern output register 44)utilizing three data “inputs” or sources, namely the lookup tables 42,the algorithmic packet/sample generation module 40, and the statemachine 30 itself. Accordingly, at block 84, the pattern generationstate machine 30 outputs pattern data 112, as determined by statetransitions programmed for the state machine 30, by combining patterndata received from the above named three sources by tracking a locationin a data sequence, transitioning to an appropriate state, and selectinga pattern output based on the current state. The pattern data 112 isshown to be output to the pattern output register 44, which is clockedby the system clock 16 to output a test pattern 114.

[0044] At block 86, the pattern generation state machine 30, uponcompletion of the output of a test pattern data sequence, resets thesequence, or progresses to the next sequence.

[0045] Exemplary Embodiment-Pattern Generator for Broadcast QualitySerial Digital Television Video

[0046]FIG. 4 is a block diagram illustrating the internal structure of apattern generator 200, according to exemplary embodiment of the presentinvention, for application in a broadcast quality serial digitaltelevision video system. The generator 200 includes componentscorresponding substantially to those of the generator 10 described abovewith reference to FIG. 1, and illustrates implementation details forthis exemplary embodiment of the present invention. The generator 200generates 16 different component video patterns for 525/625 line systemsrunning at 13.5 megahertz and 18 megahertz luminance samplingfrequencies.

[0047] In digital television video, broadcast quality test patternssuitable for testing digital television video systems and devices aretypically required. The video raster (also termed a “frame”) issynchronously reconstructed from stored 10-bit binary words, accordingto a preset sequence and timing. The sequencing is controlled by thepreprogrammed pattern generation state machine 30. The timing for thestate machine 30 is derived from an external system clock 16 (e.g., ahigh stability master clock source in host video equipment or a plantfacility). The stored 10-bit binary words are the various data elementsthat are required to construct both the visual and nonvisual pictureelements forming the raster. The picture raster consists of: (1)assemblages of picture element words forming the visible and nonvisible(timing and control) horizontal picture lines; (2) collections ofpicture lines organized into picture fields; and (3) two or more fieldsassembled and interlaced to form a picture frame (or raster). Thepicture elements comprise: (1) the timing reference signals(synchronized elements); (2) picture chrominance (color); and (3)luminance (brightness) sample values for every pixel; and (4) othernon-visible or ancillary data element values.

[0048] The exemplary embodiment of the present invention illustrated inFIG. 4 organizes and builds, from a small number of stored digitalwords, a complete television video picture that can be used for testingand/or evaluation of digital television video processing equipment.

[0049]FIG. 5 illustrates exemplary sample values, contained inrespective tables 220, that may be utilized by the generator 200illustrated in FIG. 4 to test different component standards.Specifically, the format of the lines for each existing component videostandards is somewhat similar, the most prominent difference being inthe number of samples of active video information and horizontalblanking. Each of the tables illustrated in FIG. 5 is shown to bedivided into five sample segments, so that each table has an integermultiple of five components. Each of the five segment sections holdsfour samples (i.e., the first four 10-bit words) that are the valuesthat are transmitted, and a fifth “repeat” value that indicates to thepattern generation state machine 30 how many times the previous samplesare to be repeatedly transmitted. A repeat counter 222, illustrated inFIG. 4, and keeps track of the number of times that the four sampleshave been transmitted. When the repeat counter 222 reaches the “repeat”value, then the pattern generation state machine 30 checks to see if theend of a line has been reached. If so, the generator 10 then determineswhether the line is the same as the previous. If so, a table lookuppointer 224 resets back to the relevant position in the appropriatetable 220, and the line transmission repeats. On the other hand, if theline determined by the pattern generation state machine 30 is to bedifferent from the previous one, then the table lookup pointer 224 skipsto the correct position in the relevant table 220, and starts generatingtest pattern data for a different line format.

[0050] In the exemplary embodiment of the generator 200 illustrated inFIG. 4, a maximum of two different line types for each pattern areprovided. The first type, namely the vertical blanking line types, iscommon to all patterns and these values are stored in a header table230. For the remaining line types, the color bars type is the mostdiverse, as there are different luminance/chrominance values for eachcolor. Nonetheless, an exemplary color table 232 is shown to utilizeonly 40 locations. Other patterns may be simpler, with a single foursample pattern being repeated for the entire frame, except for thevertical blanking lines. A reference black pattern may be even simpler,as it is substantially the same as the vertical blanking pattern, andtherefore no extra sample data is required for its generation. In FIG.5, an exemplary line index table 234 indicates when the generator 200should switch to and from transmitting vertical blanking lines to activevideo data lines. In FIG. 4, a line counter 236 is shown to track thenumber of lines transmitted, and compares a number of transmitted linesagainst the values in the line index table 234 to determine when toswitch line types.

[0051] In summary, patterns for the four component standards discussedabove exhibit substantial similarities, and only differ in the number ofsamples in the active video line or horizontal blanking. Accordingly, itis apparent from the tables 220 shown in FIG. 5 that only the repeatvalues differ in the various tables 220 for different standards. Ofcourse there may be a number of exceptions, an example being theequalizer pathological pattern at the 27 megahertz rate.

[0052] The execution of complex sequences of test data, utilizingreduced supplied data, is facilitated by the pattern generation statemachine 30 that controls indexing of the pointers to ensure that thecorrect data is transmitted. FIG. 6 is a flowchart illustrating aprogrammed flow sequence 240, according to an exemplary embodiment ofthe present invention, that may be implemented by the generator 200illustrated in FIG. 4.

[0053] Built-in-Self-Test (BIST) Functionality

[0054] As illustrated in FIGS. 1 and 4, the exemplary generators 10 and200 include BIST components. Checksum generation and verification(signature analysis) are widely used to implement BIST. However, thedata utilized to generate a checksum is typically provided from apseudorandom generator, and may be of little direct relevance to a user.Further, most communication systems include some form of Error Detectionand Handling (EDH) circuitry.

[0055] One embodiment of the present invention proposes utilizing suchEDH circuitry, in conjunction with a generator 10 or 200 supplying inputto the EDH circuitry, to perform a device or system test. Specifically,while a stream or packet of test data is propagated through a system, anerror check is concurrently generated to perform a complete go/no-gotest of the system. The output test data (e.g., a test pattern) of agenerator 10 or 200 is, in one embodiment, introduced as input to asystem hosting a device (e.g., a communications device). The test datais processed through the system, and concurrently through a checksumgenerator of the system, for a fixed interval, or number of words of thetest data (e.g., a test pattern). The checksum generator utilizes astandard algorithmic process, implemented in hardware, to compute one ormore checksums based on the test data being processed. The checksumscomputed by the checksum generator are then compared to pre-computedchecksum values stored in a comparator system that is, in oneembodiment, incorporated within a generator 10 or 200. Agreement betweenthe computed and stored checksum values indicates that a host system,and a device included within such a host system (e.g., a communicationsdevice), are functioning correctly. Detection of one more incorrectchecksums indicates a failure of one or more components of a hostsystem.

[0056] The present invention is advantageous in that the operationsperformed by the BIST components and the pattern generation systems arerun concurrently (or in parallel), and this allows the test datautilized to feed the BIST components also to be utilized for functionalverification (e.g., by observation of an output of the circuit) of acircuit and/or a device or system incorporating such as circuit. Inother words, one embodiment of the present invention contemplates thattest data be concurrently provided to a circuit for the purposes offunctional verification and to BIST components to facilitatebuilt-in-self-test of a device or system.

[0057]FIG. 7 is a flowchart illustrating a method 260, according to anexemplary embodiment of the present invention, of performing a BISToperation, the BIST operation being performed concurrently with afunctional verification of a circuit or device.

[0058] The method 260 assumes that a circuit is placed in a BIST mode byassertion of an appropriate test mode number input signal 280, indicatedin FIG. 1. The method 260 then commences at block 262 with the assertionof a perform checksum test signal 282, which is input to the BIST statemachine 46. The generator 10 is reset at block 264, responsive to theassertion of the perform checksum test signal 282, and a command toperform a built-in self-test is placed on the pattern output signal 114at block 266. The command is a signal that indicates data being returnedhas the checksum in this position for comparison. At selected points inthe test data output as the pattern output signal 114 (e.g., at the endof a sequence), the BIST state machine 46 initiates a checksumcomparison, as indicated at block 268 in FIG. 7. Specifically, thechecksum as output from a device or system under test is presented as aninput on a test pattern data bus 284, shown in FIG. 1, at block 270 andcompared with an expected checksum 286 retrieved from the lookup tablesfor BIST 48 at block 272. The expected checksum 286 is output from thelookup tables 48 responsive to the assertion of a selected expectedchecksum signal 288 generated by the BIST state machine 46. The expectedchecksum 286 and the test pattern data retrieved from the bus 284 areshown in FIG. 1 to be input into a comparator 52, which outputs achecksum comparison signal 290 to the BIST state machine 46.

[0059] At block 274, the BIST state machine 46, responsive to thechecksum comparison signal 290, asserts set/clear BIST pass/fail signals292 that provides input to the BIST register 54 that in turn outputs aBIST pass/fail signal 294.

[0060] Referring now specifically to the exemplary generator 200illustrated in FIG. 4, this exemplary digital video televisionembodiment is illustrated to have a specific implementation of thebuilt-in self-test (BIST) component structure illustrated in FIG. 1. TheBIST components illustrated in FIG. 4 allow a comprehensive checking ofa digital video television system without the need for expensive testequipment. Specifically, a system under test may utilize two testpatterns, supplied by the generator 10 as pattern output signals 114, asa data source. The system under test, utilizing incorporated EDHcircuitry, generates EDH cyclic redundancy check (CRC) check wordsassociated with this input data. The generated check words are thencompared against the computed and stored values (i.e., expectedchecksums) in a manner described above to determine whether the systemunder test is operating as expected. If the checksums match, the BISTpass/fail signal 294 is set to “1”, indicating a successful BISToperation. If this signal is not asserted for a predetermined timeperiod after initiating the BIST operation, then the system under testis deemed to be operationally faulty.

[0061]FIG. 8 is at block diagram illustrating a further detailsregarding an exemplary comparator system 52 that may be utilized toimplement the exemplary embodiment described immediately above.

[0062]FIG. 9 is a flowchart illustrating a programmed method 300,according to an exemplary embodiment of the present invention, accordingto which the BIST state machine 46 of the exemplary generator 200 shownin FIG. 4 may operate.

[0063] Testing of Transmit, Channel and Receive Units

[0064]FIG. 10 is a block diagram illustrating an arrangement by which acomplete test of transmit, channel and receive units of an exemplarycommunications device 340 may be performed. Specifically, for functionaltesting, a set of patterns that are verifiable by an observation systemmust be determined. To commence a complete test of the device 340, thedevice 340 is placed in a pattern generation mode by assertion of anappropriate signal as the test mode number input signal 280. A suitableclock is applied as the system clock 16, and the output of a receiver ofthe device 340 is observed and monitored. In one embodiment, noadditional test equipment is required. The observing system may performany operations that are suited to decoding the received data, such as astraight forward comparison of the supplied and received patterns. Othermethods of verification utilize a visual verification (e.g., for videochannels), control systems (e.g., where the transmitted patterninstructs an observing unit to perform task) and data analysis systems(e.g., where the stream and/or packets of test data are evaluated todetermine the validity thereof).

[0065] Considering specifically the testing of a digital televisionvideo device, such a device is typically placed in one of multiplepattern generation modes (e.g., a PAL color bar mode) and an appropriateclock signal is applied. The outputs of the digital television videodevice is then connected to a SMPTE 259M compatible picture monitor,whereafter the functionality of the device may be verified if color barsare displayed. Simultaneously, the BIST components of the generator 10examine the internal logic status for the device, and the result of theBIST may be observed utilizing a test-out pin.

[0066] In a summary, after test data, for example in the form of testpatterns generated by a pattern generator 10, is applied to a device orsystem, the following aspects of the system may be verified:

[0067]1. The functionality of a physical layer (e.g., the portion of thesystem that drives data onto a communications channel);

[0068]2. The functionality of modulator logic (e.g., by checking theoutput data and by looking at a BIST result pin);

[0069]3. The functionality of a receiver, and the compatibility thereofwith a communications standard or system;

[0070]4. The system functionality by verifying the input controlsproperly control the device, and that the device is operating at fullspeed; and

[0071]5. A high level of fault coverage by performance of fault analysisof output data.

[0072] Integrated Circuit

[0073]FIG. 11 is at block diagram illustrating an integrated circuit360, according to an exemplary embodiment of the present invention, thatincorporates a test pattern generator 10 with integrated BIST controlcircuitry. Specifically, the integrated circuit 360 comprises a digitaltelevision video parallel-to-serial data converter having built-inself-test functionality and test pattern generation system. The testpattern generation system incorporates an algorithmic digital televisionvideo test pattern generator 10, a digital television video checksumgenerator 362 and a comparator with precomputed, stored checksum valuesfor the algorithmic test patterns. The test pattern generation system isutilized to perform a complete go/no-go test of the integrated circuit316, including a test of all subsystem elements that are illustrated inFIG. 11.

[0074] Thus, an algorithmic test pattern generator, withbuilt-in-self-test (BIST) capabilities to verify a circuit and a systemincluding such a circuit, and a method of operating such an algorithmictest pattern generator, have been described. Although the presentinvention has been described with reference to specific exemplaryembodiments, it will be evident that various modifications and changesmay be made to these embodiments without departing from the broaderspirit and scope of the invention. Accordingly, the specification anddrawings are to be regarded in an illustrative rather than a restrictivesense.

What is claimed is:
 1. A method of generating test data to functionallyverify a circuit, the method comprising: detecting a data selectionsignal; responsive to the data selection signal, presenting test data toverify the circuit, wherein the presenting of the test data includescomposing the test data utilizing a combination of algorithmicallygenerated data and stored data.
 2. The method of claim 1 wherein thecomposing of the test data is performed utilizing state machinegenerated data.
 3. The method of claim 1 wherein the presenting of thetest data is performed under the control of a state machine.
 4. Themethod of claim 1 wherein the test data comprises a data stream.
 5. Themethod of claim 4 wherein the data stream comprises a video test patternto functionally test a video device.
 6. The method of claim 1 whereinthe test data comprises a plurality of packets of data.
 7. The method ofclaim 1 wherein the test data is supplied to a system to testfunctionality of the system.
 8. The method of claim 7 wherein the systemis a video display system.
 9. The method of claim 8 wherein the videodisplay system comprises any one of a group of including a SMPTE-259M,SMPTE-292M and a Digital Video Interface (DVI) device.
 10. The method ofclaim 1 further comprising utilizing the test data to perform built-inself-test of the circuit in parallel with the functional verification ofthe circuit.
 11. The method of claim 10 further comprising feeding thetest data to the circuit and to a checksum generator circuit.
 12. Themethod of claim 11 further comprising comparing an output of thechecksum generator circuit to an expected checksum.
 13. The method ofclaim 12 wherein the comparison is performed at a selected point withinthe test data.
 14. The method of claim 1 wherein the circuit comprisespart of a host system, and the test data is fed to the host system. 15.The method of claim 14 wherein the host system comprises a digitaltelevision system.
 16. A test circuit to generate test data tofunctionally verify a subject circuit, the test circuit comprising: aselection input to receive a data selection signal; a test datagenerator, responsive to the data selection signal, to output test datato verify the circuit, wherein the test data generator is to compose thetest data utilizing a combination of algorithmically generated data andstored data.
 17. The test circuit of claim 16 wherein the test datagenerator is to compose the test data utilizing state machine generateddata.
 18. The test circuit of claim 16 wherein presentation of the testdata is performed under the control of a state machine of the test datagenerator.
 19. The test circuit of claim 16 wherein the test datacomprises a data stream.
 20. The test circuit of claim 19 wherein thedata stream comprises a video test pattern to functionally test a videodevice.
 21. The test circuit of claim 16 wherein the test data comprisesa plurality of packets of data.
 22. The test circuit of claim 1 furthercomprising a test data output to supply the test data to a system totest functionality of the system.
 23. The test circuit of claim 22wherein the system is a video display system.
 24. The test circuit ofclaim 23 wherein the video display system comprises any one of a groupof including a SMPTE-259M, SMPTE-292M and a Digital Video Interface(DVI) device.
 25. The test circuit of claim 16 further comprisingbuilt-in self-test circuitry to utilize the test data to perform abuilt-in self-test of the circuit in parallel with the functionalverification of the subject circuit utilizing the output of the subjectcircuit generated responsive to the input of the test data.
 26. The testcircuit of claim 25 further comprising feeding the test data to thecircuit and to a checksum generator circuit.
 27. The test circuit ofclaim 26 further comprising comparing an output of the checksumgenerator circuit to an expected checksum.
 28. The test circuit of claim27 wherein the comparison is performed at a selected point within thetest data, the selected point being determined by a state machine. 29.The test circuit of claim 16 wherein the subject circuit comprises partof a host system, and the test data is fed to the host system.
 30. Thetest circuit of claim 14 wherein the host system comprises a digitaltelevision system.
 31. A method of testing a circuit comprising:providing test data to the circuit, the test data functionally to verifythe circuit, wherein the functional verification of the circuit isperformed utilizing an output of the circuit generated responsive to thetest data in accordance with operational functionality of the circuit;and providing the test data to a built-in self-test (BIST) circuit inparallel with the provision thereof to the circuit, wherein the built-inself-test generates a BIST output responsive to the test data.
 32. Themethod of claim 31 wherein the built-in self-test circuit includes achecksum generator, and the method includes comparing an output of thechecksum generator to an expected checksum.
 33. The method of claim 32including retrieving the expected checksum from storage associated withthe built-in self-test circuit.
 34. The method of claim 33 comprisingretrieving the expected checksum from a lookup table.
 35. The method ofclaim 32 wherein the built-in self-test circuit includes a built-inself-test state machine.
 36. The method of claim 35 wherein the built-inself-test state machine initiates the comparison of the output of thechecksum generator to the expected checksum at a selected point in thetest data.
 37. The method of claim 31 wherein the functionalverification is performed utilizing an output of a system including thecircuit.
 38. The method of claim 37 wherein the system comprises adigital video device, and where the output of the system is viewable ona video display to functionally verify the system.
 39. The method ofclaim 38 wherein the output defines a test pattern.
 40. A test systemcomprising: a test data generator to provide test data to a subjectcircuit, the test data functionally to verify the subject circuit,wherein the functional verification of the subject circuit is performedutilizing an output of the subject circuit generated responsive to thetest data in accordance with operational functionality of the subjectcircuit; and a built-in self-test (BIST) circuit to receive the testdata concurrently with the provision thereof to the subject circuit. 41.The test system of claim 40 wherein the built-in self-test circuitincludes a checksum generator and compares an output of the checksumgenerator to an expected checksum.
 42. The test system of claim 41wherein the built-in self-test circuit is to retrieve the expectedchecksum from storage associated with the built-in self-test circuit.43. The test system of claim 42 wherein the built-in self-test circuitis to retrieve the expected checksum from a lookup table.
 44. The testsystem of claim 40 wherein the built-in self-test circuit includes abuilt-in self-test state machine.
 45. The test system of claim 41wherein the built-in self-test state machine is to initiate a comparisonof the output of the checksum generator to the expected checksum at aselected point in the test data.
 45. The test system of claim 40 whereinthe functional verification is performed utilizing an output of a systemincluding the subject circuit.
 46. The test system of claim 45 whereinthe system comprises a digital video device, and where the output of thesystem is viewable on a video display to functionally verify the system.47. The test system of claim 46 wherein the output defines a testpattern.
 48. A method of manufacturing a test circuit to generate testdata to functionally verify a subject circuit, the method comprising:constructing a selection input to receive from a data selection signal;coupling a test data composer to an algorithmic data generator and to adata storage unit, coupling the selection input to a test data generatorso as to enable the test data composer, responsive to the data selectionsignal, to output test data to verify the circuit, the test datagenerator to compose the test data utilizing a combination ofalgorithmically generated data retrieved from the algorithmic datagenerator and stored data retrieved from the data storage unit.
 49. Amethod of manufacturing a test system, the method comprising: providinga test data generator to provide test data to a subject circuit, thetest data functionally to verify the subject circuit, wherein thefunctional verification of the subject circuit is performed utilizing anoutput of the subject circuit generated responsive to the test data inaccordance with an operational functionality of the subject circuit; andcoupling the test data generator to a built-in self-test (BIST) circuitso as to enable the built-in self-test circuit to receive the test dataconcurrently with the provision thereof to the subject circuit.